Microprocessor & Interfacing
Subject Code: 20CST-252 — University Institute of Engineering, Department of CSE. Complete interactive study resource covering every topic from your syllabus.
Introduction to Microprocessor
1.1 Definition and Fundamentals
A microprocessor (MP or μP) is a multipurpose, programmable, clock-driven, register-based electronic device fabricated on a single integrated circuit (IC). It reads binary instructions from a storage device called memory, accepts binary data as input, processes data according to those instructions, and provides output. It is also known as the CPU (Central Processing Unit) and is the heart of any computer system.
The microprocessor is a complete computation engine built with thousands (now billions) of transistors on a single chip. As technology has progressed, microprocessors have become faster, smaller, and capable of doing more work per clock cycle. Modern processors contain billions of transistors on chips smaller than a fingernail.
General Architecture of a Microprocessor
Internally, every microprocessor is made up of three main functional units:
- Arithmetic Logic Unit (ALU): Performs all arithmetic operations (addition, subtraction, increment, decrement) and logical operations (AND, OR, XOR, NOT, shift, compare). It takes data from registers, processes it, and stores results back in registers (typically the accumulator).
- Control Unit (CU): The brain of the microprocessor that coordinates all activities. It fetches instructions from memory, decodes them, and generates appropriate timing and control signals to execute them. It does not process data itself but directs the flow of data between the ALU, registers, memory, and I/O devices.
- Register Array: A set of high-speed storage locations inside the processor that hold data being currently processed. Registers are the fastest memory in the system — much faster than RAM. They include general-purpose registers, the accumulator, and special-purpose registers like the Program Counter and Stack Pointer.
1.2 Characteristics of a Microprocessor
The capabilities and limitations of a microprocessor are defined by its key characteristics. Understanding these is essential for comparing different processors.
| Characteristic | Description | 8085 Example |
|---|---|---|
| Data Bus Size | Number of bits that can be transferred simultaneously. Determines how much data the processor can handle in one operation. | 8-bit (D0–D7) |
| Address Bus Size | Number of bits used to address memory locations. Determines maximum addressable memory: Memory = 2n where n = address lines. | 16-bit (A0–A15) → 64 KB |
| Word Length | The maximum number of bits a processor can process in a single operation. Often equals data bus width but can differ. | 8-bit |
| Clock Speed | Number of clock cycles per second (MHz/GHz). Higher clock speed generally means faster execution. Measured in frequency. | 3 MHz |
| Instruction Set | The complete set of instructions a processor can execute. Includes data transfer, arithmetic, logical, branch, and control instructions. | 74 instructions |
| I/O Addressing | Method used to address I/O devices: memory-mapped I/O or isolated I/O. Determines how peripherals communicate. | Isolated I/O (256 ports) |
| Data Types | Types of data the processor can handle: binary, BCD, ASCII, signed/unsigned integers. | Binary, BCD |
Memory Calculation Explorer
Adjust the number of address lines to see the addressable memory.
1.3 Microprocessor vs Microcomputer vs Microcontroller
These three terms are frequently confused but represent fundamentally different things. A microprocessor is just the CPU chip, a microcomputer is a complete computer built around a microprocessor, and a microcontroller is a self-contained system-on-a-chip designed for control applications.
| Feature | Microprocessor | Microcomputer | Microcontroller |
|---|---|---|---|
| Definition | Single IC that functions as CPU | Complete computer with MP, memory, I/O on PCB | IC with MP, memory, I/O, timers all on one chip |
| Components | ALU, CU, Registers only | MP + RAM + ROM + I/O ports + motherboard | MP + RAM + ROM + I/O + Timers + ADC/DAC |
| Memory | External (separate chips) | External (separate chips on board) | Internal (on-chip) |
| I/O Ports | External interface needed | On motherboard | Built-in on chip |
| Application | General-purpose computing | Personal computers, workstations | Embedded systems, appliances, automotive |
| Power | Higher power consumption | Moderate to high | Very low power |
| Cost | Moderate (need external parts) | Higher (full system) | Low (single chip solution) |
| Speed | Very high (GHz range) | High | Lower (MHz range) |
| Flexibility | Highly flexible, customizable | Moderately flexible | Less flexible, application-specific |
| Example | Intel 8085, Pentium, Core i7 | Desktop PC, Laptop | 8051, AVR, PIC, ARM Cortex-M |
1.4 System Bus and Its Types
A system bus is a group of wires (parallel electrical lines) that carry signals between the microprocessor, memory, and I/O devices. It is the communication backbone of the computer system — all data, addresses, and control signals travel through these buses.
Data Bus
- Collection of wires that transmit actual data (not addresses).
- Size is called width — common widths: 8, 16, 32, 64 bits.
- A 16-bit data bus processor is roughly double the speed of an 8-bit processor for the same clock, because it transfers twice the data per cycle.
- Bidirectional — data flows both ways: MP → Memory/I/O (write) and Memory/I/O → MP (read).
- Number of I/O ports = 2data bus width. For 8-bit bus: 28 = 256 ports.
Address Bus
- Carries the address of the memory location or I/O port the MP wants to access.
- Unidirectional — addresses always flow FROM the microprocessor TO memory/I/O devices (only the MP generates addresses).
- Width directly determines memory capacity: Memory = 2n bytes, where n = number of address lines.
- 8085 has 16 address lines → 216 = 65,536 = 64 KB addressable memory.
Control Bus
- Carries control signals that coordinate and synchronize all operations.
- Individual lines can be unidirectional or bidirectional depending on the signal.
- Key signals:
| Signal | Type | Purpose |
|---|---|---|
RD | Output, Active Low | Indicates MP wants to read data from memory/I/O |
WR | Output, Active Low | Indicates MP wants to write data to memory/I/O |
IO/M | Output | Differentiates I/O operation (1) from Memory operation (0) |
ALE | Output | Address Latch Enable — indicates valid address on AD0-AD7 |
Bus Organization Applications
Address bus sends the target location, data bus transfers the data to be stored/retrieved. Essential for instruction fetching and data manipulation.
Address bus sends the device/port address, data bus transfers input/output data. Enables communication with keyboards, displays, sensors, etc.
Control bus carries interrupt signals. Address bus fetches the interrupt vector, data bus fetches the interrupt service routine from memory.
Direct Memory Access allows data transfer between memory and I/O without MP intervention. Bus is relinquished via HOLD/HLDA signals.
Click a scenario to see which bus signals activate.
Unit 1 — Practice Questions
Architecture of 8085 Microprocessor
2.1 Introduction to Intel 8085
The Intel 8085 is an 8-bit microprocessor introduced by Intel in 1976. It was one of the most widely used microprocessors in academic and industrial applications and remains a foundational subject in computer engineering education.
| Feature | Specification |
|---|---|
| Data Bus | 8-bit (D0–D7) |
| Address Bus | 16-bit (A0–A15) |
| Multiplexed Bus | AD0–AD7 (lower 8 address lines multiplexed with data) |
| Addressable Memory | 216 = 64 KB |
| I/O Addressing | 8-bit → 28 = 256 I/O ports |
| Transistors | 6,200 |
| Power Supply | +5V at VCC, Ground at VSS |
| Clock Frequency | 3 MHz (internal clock generator) |
| Instructions | 74 instructions |
| Addressing Modes | 5 modes |
| Interrupts | 5 hardware + 8 software |
| Control Signals | 12 control signals |
| Serial I/O | SID (Serial Input Data) and SOD (Serial Output Data) |
| Package | 40-pin DIP (Dual In-line Package) |
Arithmetic and Logical Operations Supported
- 8-bit binary addition (with/without carry)
- 16-bit binary addition
- 2-digit BCD addition
- 8-bit subtraction (with/without borrow)
- Increment / Decrement of 8-bit data
- Logical AND, OR, EX-OR
- Complement (1's and 2's)
- Rotate operations (left/right with/without carry)
2.2 Processing Unit: ALU, Accumulator, Flags
Accumulator (Register A)
An 8-bit register that is part of the ALU. After every arithmetic or logical operation, the result is stored in the accumulator. Most instructions implicitly use the accumulator as one operand. It is the most frequently used register in 8085.
Arithmetic and Logic Unit (ALU)
Performs arithmetic operations (ADD, SUB, INC, DEC) and logical operations (AND, OR, XOR, NOT, compare) on data from the accumulator and temporary register. Results are stored back in the accumulator. The ALU also updates the flag register based on the result.
Temporary Register
An 8-bit register that holds the second operand during ALU operations. It is invisible to the programmer — you cannot directly read or write to it. When you execute ADD B, the contents of register B are first copied to the temporary register, then the ALU adds accumulator and temporary register contents.
Flag Register
The flag register is a special-purpose 8-bit register where only 5 bits are used. These flags are set (1) or reset (0) after ALU operations based on the result. The flag register + accumulator together form the Program Status Word (PSW).
| Flag | Bit | Set (1) When | Reset (0) When | Accessible? |
|---|---|---|---|---|
| Sign (S) | D7 | Result is negative (MSB = 1) | Result is positive (MSB = 0) | Yes |
| Zero (Z) | D6 | Result is zero (all bits = 0) | Result is non-zero | Yes |
| Auxiliary Carry (AC) | D4 | Carry from bit D3 to D4 | No carry from D3 to D4 | No (internal) |
| Parity (P) | D2 | Even number of 1s in result (even parity) | Odd number of 1s in result (odd parity) | Yes |
| Carry (CY) | D0 | Carry out of MSB (result > 8 bits) | No carry out | Yes |
Enter two 8-bit hex values and an operation to see which flags get set.
2.3 Instruction Unit and Control Unit
Instruction Register (IR)
An 8-bit register that holds the current instruction (opcode) fetched from memory. The microprocessor decodes and executes whatever is stored in the IR. The programmer cannot directly access this register.
Instruction Decoder
Interprets the instruction stored in the IR. It identifies what operation is to be performed and on what data. Based on the decoded instruction, it generates specific machine cycles that are sent to the Timing and Control Unit.
Timing and Control Unit
This is the master controller of the 8085. It:
- Receives machine cycle information from the instruction decoder.
- Generates 12 control signals that coordinate all processor operations.
- Provides timing signals synchronized with the clock (3 MHz).
- Controls data flow between the processor, memory, and I/O devices through the system bus.
- Manages the sequence of T-states within each machine cycle.
2.4 Storage and Interface Unit: Registers
General Purpose Registers (B, C, D, E, H, L)
Six 8-bit registers used to store temporary data during program execution. They can be used individually as 8-bit registers or combined as register pairs for 16-bit operations:
Register Pair
Register Pair
Register Pair (Pointer)
The H–L pair is special — it is commonly used as a memory pointer. When an instruction uses "M" as an operand, it refers to the memory location whose address is stored in the H–L register pair.
Special Purpose Registers
| Register | Size | Purpose |
|---|---|---|
| Program Counter (PC) | 16-bit | Stores the address of the next instruction to be fetched. Automatically incremented after each byte fetch. Used for sequential execution and branch operations. |
| Stack Pointer (SP) | 16-bit | Points to the top of the stack in R/W memory. Stack grows downward. Used during subroutine calls (CALL/RET) and interrupt handling to save/restore the PC. |
Other Components
- Increment/Decrement Register: Holds the 16-bit address that needs to be incremented or decremented by 1 (used by INX, DCX instructions).
- Address Latch: Stores the upper-order byte (A8–A15) of the 16-bit address during bus operations.
- Address/Data Latch: Stores either the lower-order address byte (A0–A7) or the 8-bit data (D0–D7) from the multiplexed AD0–AD7 bus.
- Serial I/O Control: Converts serial data to parallel for the microprocessor and parallel data to serial for peripheral devices. Controls SID and SOD lines.
- Interrupt Controller: Handles all 5 hardware interrupts (TRAP, RST7.5, RST6.5, RST5.5, INTR) according to their priority levels.
Unit 2 — Practice Questions
Pin Diagram, Interrupts & Addressing Modes
3.1 Interrupts and Their Types
An interrupt is a signal that causes the microprocessor to temporarily stop its current execution and jump to a special subroutine (Interrupt Service Routine). After executing the ISR, the processor returns to the previous program exactly where it left off.
Interrupt Handling Sequence
- Complete execution of the current instruction
- Save PC contents onto the stack (PUSH PC)
- Load PC with the address of the ISR (interrupt vector)
- Execute the Interrupt Service Routine
- Return to previous program by reading top of stack (RET instruction pops PC)
Hardware Interrupts of 8085
| Interrupt | Maskable? | Vectored? | Trigger | Priority | Vector Address |
|---|---|---|---|---|---|
| TRAP | Non-maskable | Vectored | Level & Edge | 1 (Highest) | 0024H |
| RST 7.5 | Maskable | Vectored | Edge triggered | 2 | 003CH |
| RST 6.5 | Maskable | Vectored | Level triggered | 3 | 0034H |
| RST 5.5 | Maskable | Vectored | Level triggered | 4 | 002CH |
| INTR | Maskable | Non-vectored | Level triggered | 5 (Lowest) | External (INTA) |
Classification of Interrupts
Maskable interrupts can be enabled or disabled by the programmer using the SIM (Set Interrupt Mask) instruction. RST 5.5, RST 6.5, RST 7.5, and INTR are maskable.
Non-maskable interrupts cannot be disabled by software. TRAP is the only non-maskable interrupt in 8085. It is used for critical events like power failure that must be handled regardless of the processor state.
Vectored interrupts automatically transfer control to a fixed, predefined memory address (the interrupt vector). The processor knows exactly where to jump without needing external hardware to supply the address. All RST interrupts and TRAP are vectored.
Non-vectored interrupts do not have a fixed vector address. INTR is non-vectored — the external device must provide the interrupt vector address through the data bus after receiving the INTA (Interrupt Acknowledge) signal from the processor.
Edge-triggered: Activated at the rising or falling edge of the signal. RST 7.5 is edge-triggered — it responds to the transition from low to high, not the sustained level. This makes it suitable for detecting transient events.
Level-triggered: Activated when the signal is held at a high level. RST 5.5, RST 6.5, and INTR are level-triggered. The interrupt signal must remain high until the processor acknowledges it.
TRAP is both edge and level triggered for maximum reliability — it responds to the rising edge AND requires the signal to remain high.
Software interrupts are invoked by executing specific instructions in the program (not by external hardware signals). The 8085 has 8 software interrupts:
| Instruction | Vector Address |
|---|---|
| RST 0 | 0000H |
| RST 1 | 0008H |
| RST 2 | 0010H |
| RST 3 | 0018H |
| RST 4 | 0020H |
| RST 5 | 0028H |
| RST 6 | 0030H |
| RST 7 | 0038H |
Trigger multiple interrupts simultaneously to see which one the 8085 handles first based on priority.
3.2 Pin Diagram of 8085 (40-Pin DIP)
The 8085 microprocessor comes in a 40-pin Dual In-line Package (DIP). Each pin serves a specific purpose. Click on any pin in the diagram below to see its description.
Key Pin Groups Summary
| Pin Group | Pins | Direction | Function |
|---|---|---|---|
| Power | VCC(40), VSS(20) | Input | +5V supply and Ground |
| Clock | X1(1), X2(2) | Input | Crystal/timing network for internal clock |
| Reset | RESET IN(3), RESET OUT(36) | In/Out | Reset processor and peripherals |
| Serial I/O | SID(4), SOD(5) | In/Out | Serial data input/output (1-bit) |
| Interrupts | TRAP(6), RST7.5(7), RST6.5(8), RST5.5(9), INTR(10) | Input | Hardware interrupt requests |
| Interrupt Ack | INTA(11) | Output | Acknowledges INTR interrupt |
| Address/Data | AD0–AD7 (12–19) | Bidirectional | Multiplexed lower address and data bus |
| Address High | A8–A15 (21–28) | Output | Upper 8 bits of address bus |
| Status | S0(29), S1(33) | Output | Machine cycle status signals |
| ALE | ALE(30) | Output | Address Latch Enable for demultiplexing |
| IO/M | IO/M(34) | Output | Selects I/O (1) or Memory (0) operation |
| Ready | READY(35) | Input | Synchronizes slow peripherals with MP |
| Hold/HLDA | HOLD(38), HLDA(39) | In/Out | DMA request and acknowledge |
| Read/Write | RD(32), WR(31) | Output | Read and Write control signals (active low) |
3.3 Addressing Modes of 8085
The method by which the address of the source operand (data) and the destination of the result is specified in an instruction is called an addressing mode. In every instruction, the programmer must specify: (1) the operation, (2) where the data comes from, and (3) where the result goes. The 8085 has 5 addressing modes.
The operand is available directly in the instruction itself. No memory or register reference is needed — the data is part of the instruction.
Format: Opcode | Data (8-bit for 2-byte instructions, 16-bit for 3-byte instructions)
MVI B, 45H ; Move 45H immediately to register B (2 bytes)
LXI H, 3050H ; Load H-L pair with 3050H immediately (3 bytes)
MVI A, FFH ; Load accumulator with FFHThe operands are stored in internal registers. The instruction specifies which registers contain the data. These are always 1-byte instructions since the register codes are embedded in the opcode.
MOV A, B ; Move contents of B to A
ADD C ; Add contents of C to A, result in A
INR A ; Increment A by 1
SUB D ; Subtract D from AThe instruction contains the 16-bit address of the memory location where the operand is stored. Always a 3-byte instruction: opcode + low address byte + high address byte.
LDA 2050H ; Load accumulator with contents of memory location 2050H
LHLD 3000H ; Load H-L pair from memory locations 3000H and 3001H
STA 4000H ; Store accumulator contents at memory location 4000H
IN 35 ; Read data from I/O port number 35The instruction specifies a register pair that contains the address of the operand. The register pair acts as a pointer to memory. "M" refers to the memory location pointed to by H-L pair.
MOV A, M ; Move contents of memory pointed by HL to accumulator
ADD M ; Add contents of memory pointed by HL to accumulator
LDAX B ; Load accumulator from memory pointed by B-C pair
STAX D ; Store accumulator to memory pointed by D-E pairThe operand location is implicitly understood from the opcode itself. No register or address needs to be specified — the instruction operates on a fixed operand (usually the accumulator). Always 1-byte instructions.
CMA ; Complement accumulator (1's complement of A)
RAL ; Rotate accumulator left through carry
RAR ; Rotate accumulator right through carry
RLC ; Rotate accumulator left (without carry in old bit)
RRC ; Rotate accumulator right (without carry in old bit)Type any 8085 instruction to identify its addressing mode.
Unit 3 — Practice Questions
Instruction Cycle, Machine Cycle & Timing Diagram
4.1 Instruction Cycle, Machine Cycle, and T-States
The complete process of fetching an instruction from memory and executing it is called one instruction cycle. The 8085 fetches and executes instructions one at a time, sequentially.
Fetch Cycle (4 T-States)
| T-State | Operation | Signals |
|---|---|---|
| T1 | PC contents (address) placed on address bus. ALE=1 to latch lower address. Status signals sent. | ALE=1, IO/M=0, S1=1, S0=1 |
| T2 | Lower address disappears from AD0-AD7. RD goes low to enable memory. | RD=0 |
| T3 | Opcode from memory placed on data bus. Loaded into Instruction Register. RD goes high. | RD=1 (deasserted) |
| T4 | Opcode sent to instruction decoder for decoding. 1-byte instructions execute in this state itself. | Internal operation |
Machine Cycle
The time required by the microprocessor to complete one operation of accessing memory or I/O is called a machine cycle. Each clock pulse is called a T-State. The number of T-states required for one machine cycle varies.
| Machine Cycle | IO/M | S1 | S0 | RD | WR | T-States |
|---|---|---|---|---|---|---|
| Opcode Fetch | 0 | 1 | 1 | 0 (T2-T3) | 1 | 4 |
| Memory Read | 0 | 1 | 0 | 0 (T2-T3) | 1 | 3 |
| Memory Write | 0 | 0 | 1 | 1 | 0 (T2-T3) | 3 |
| I/O Read | 1 | 1 | 0 | 0 (T2-T3) | 1 | 3 |
| I/O Write | 1 | 0 | 1 | 1 | 0 (T2-T3) | 3 |
4.2 Timing Diagrams with Examples
Timing Diagram for Opcode Fetch
Worked Examples
MOV A, C is a 1-byte instruction stored at a single memory location (e.g., 0011H). Only an Opcode Fetch machine cycle is needed — 4 T-states total.
| T-State | ALE | RD | WR | IO/M | S0 | S1 | AD0-AD7 |
|---|---|---|---|---|---|---|---|
| T1 | 1 | 1 | 1 | 0 | 1 | 1 | 11H (lower addr) |
| T2 | 0 | 0 | 1 | 0 | 1 | 1 | Opcode on bus |
| T3 | 0 | 0 | 1 | 0 | 1 | 1 | Opcode loaded in IR |
| T4 | 0 | 1 | 1 | 0 | 1 | 1 | Decode & Execute |
MVI C, 00H is a 2-byte instruction. Stored at 0007H (opcode) and 0008H (data 00H). Requires two machine cycles:
M1: Opcode Fetch — 4 T-states (fetch MVI C opcode from 0007H)
M2: Memory Read — 3 T-states (read operand 00H from 0008H)
Total: 7 T-states
| Instruction | Bytes | Machine Cycles | T-States |
|---|---|---|---|
| MVI A, 35H | 2 | OF + MR | 4 + 3 = 7 |
| MVI B, 23H | 2 | OF + MR | 4 + 3 = 7 |
| ADD B | 1 | OF | 4 |
| Total | 5 | 5 cycles | 18 |
Select instructions to calculate total bytes and T-states.
Unit 4 — Practice Questions
Programmable Logic Devices (PLDs)
5.1 Introduction to PLDs and Types
A PLD is an electronic component used to build reconfigurable digital circuits. Unlike fixed-function logic gates (where the circuit is determined at manufacture), PLDs can be programmed by the user to implement any combinational or sequential logic function. They contain arrays of AND and OR gates whose connections can be programmed (made or broken).
Types of PLDs
| PLD Type | AND Array | OR Array | Flexibility | Use Case |
|---|---|---|---|---|
| PROM | Fixed | Programmable | Low | Memory, lookup tables |
| PAL | Programmable | Fixed | Medium | Combinational logic, simple state machines |
| PLA | Programmable | Programmable | High | Complex combinational logic with minimized terms |
| FPGA | Full programmable fabric | Full programmable fabric | Very High | Complex systems, DSP, processors |
| GAL | Programmable | Fixed (with macrocells) | High | Reprogrammable alternative to PAL |
Advantages of PLDs
- Design flexibility: Can be reprogrammed to change functionality without changing hardware.
- Reduced board space: One PLD can replace dozens of individual logic ICs.
- Faster prototyping: Design changes are made in software, not by rewiring hardware.
- Cost effective: For medium-volume production, PLDs are cheaper than custom ASICs.
- Reliability: Fewer components on the board means fewer points of failure.
- Security: Some PLDs support security bits to prevent unauthorized copying of designs.
Disadvantages of PLDs
- Speed: PLDs are generally slower than custom ASICs due to programmable interconnect delays.
- Power consumption: Higher than optimized discrete logic for simple functions.
- Learning curve: Requires knowledge of HDLs (VHDL, Verilog) and PLD programming tools.
- Limited capacity: Smaller PLDs cannot implement very complex designs (unlike FPGAs).
5.2 PLA — Programmable Logic Array
A Programmable Logic Array has both the AND array and the OR array programmable. This dual programmability allows for logic minimization — you only implement the product terms you actually need, making efficient use of the chip's resources.
PLA Architecture
Numerical Example: Implement F = AB + A'C using PLA
Given: F = AB + A'C (3 inputs: A, B, C)
Step 1 — Identify product terms: P1 = AB, P2 = A'C
Step 2 — Program AND array: Connect A and B inputs to AND gate for P1. Connect A' and C inputs to AND gate for P2.
Step 3 — Program OR array: Connect both P1 and P2 outputs to a single OR gate for output F.
Step 4 — PLA size: 3 inputs × 2 product terms × 1 output → 3 × 2 × 1 PLA
5.3 PAL — Programmable Array Logic
A Programmable Array Logic device has a programmable AND array but a fixed (hardwired) OR array. The OR connections are predetermined at manufacture — each output has a fixed number of AND terms OR-ed together.
PLA vs PAL Comparison
| Feature | PLA | PAL |
|---|---|---|
| AND Array | Programmable | Programmable |
| OR Array | Programmable | Fixed (hardwired) |
| Flexibility | Higher — any product term can go to any output | Lower — fixed number of terms per output |
| Speed | Slightly slower (two programmable levels) | Faster (only one programmable level) |
| Cost | More expensive | Less expensive |
| Design Complexity | Requires full minimization for both arrays | Simpler — only AND array needs programming |
| Number of Product Terms | Shared across all outputs | Fixed per output (e.g., 4-8 terms per OR gate) |
| Logic Minimization | Essential — fewer terms save chip resources | Less critical — each output has dedicated terms |
| Example Device | PLA16L8 | PAL16L8, PAL22V10 |
5.4 Field Logic Array (FLA) and Applications
A Field Logic Array is a broader category of programmable logic devices that can be configured "in the field" (i.e., by the end user, not at the factory). FLAs include PLAs, PALs, GALs, and FPGAs. The term emphasizes that the logic function is determined after the chip is manufactured — during field programming.
FLA vs Discrete Logic Circuits
| Aspect | Discrete Logic (74xx ICs) | FLA-based Design |
|---|---|---|
| Design Method | Manual schematic with individual gates | HDL-based design, synthesized into PLD |
| Board Space | Many ICs needed for complex logic | Single chip replaces many ICs |
| Modification | Requires physical rewiring/replacement | Reprogram the chip — no hardware change |
| Prototyping | Slow — breadboard, PCB changes | Fast — simulate in software, program in minutes |
| Power | Lower per gate but more ICs | Single chip, potentially lower total power |
| Speed | Very fast (dedicated gates) | Slightly slower (programmable routing delays) |
| Cost (low volume) | Higher (many ICs + larger board) | Lower (one chip + smaller board) |
| Cost (high volume) | Lower (standard parts) | Higher (PLD more expensive than simple gates) |
| Reliability | Lower (more connections, more failure points) | Higher (fewer components and connections) |
Importance of AND-OR Plane Programmability in PLA
The dual programmability of PLA provides unique advantages:
- Product term sharing: The same product term can be used by multiple outputs. For example, if AB is needed in both F1 and F2, it's generated once in the AND array and connected to both OR gates — saving resources.
- Optimal use of chip area: Since both arrays are programmable, you only implement exactly what the logic requires — no wasted product terms or fixed limitations.
- Supports complex multi-output functions: Unlike PAL where each output has a fixed number of terms, PLA can allocate terms dynamically based on actual need.
- Enables logic minimization benefits: K-map or Quine-McCluskey minimization directly translates to fewer programmed connections, smaller chip size, and lower power.
Practical Limitations of PLA and PAL
- Limited number of inputs/outputs: Traditional PLAs/PALs have fixed pin counts (16 or 24 pins), limiting the complexity of functions they can implement.
- Limited product terms: PALs restrict the number of AND terms per output (typically 4-8). Complex functions may exceed this limit.
- No sequential logic in basic PALs: Standard PALs implement only combinational logic. Registered PALs add flip-flops but with limited flexibility.
- One-time programmable (OTP): Most PALs and PLAs use fuse-based programming — once programmed, they cannot be changed. EEPROM-based GALs solved this.
- Propagation delay: Programmable connections add RC delay compared to fixed metallization in ASICs.
- Obsolescence: Many specific PLA/PAL part numbers are now obsolete, replaced by FPGAs and CPLDs.
Real-World Applications of FLA/PLA
| Application | Why FLA/PLA is Preferred |
|---|---|
| Code converters (Binary to Gray, BCD to 7-segment) | Multiple outputs sharing product terms — PLA's term sharing is ideal |
| Address decoders in memory systems | Fixed combinational logic, easy to modify for different memory maps |
| Industrial control systems | Custom logic for sensor interfacing, timing, and sequencing |
| Automotive electronics | Single chip replaces many gates, reduces board space in constrained environments |
| Peripheral interface controllers | Custom I/O decoding and control signal generation |
| Prototyping before ASIC design | Validate logic in PLD before committing to expensive ASIC fabrication |
| Consumer electronics (TVs, appliances) | Cost-effective custom logic without full ASIC development cost |
Unit 5 — Practice Questions
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